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Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs
AD5722/AD5732/AD5752
FEATURES
Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) Operates from single/dual supplies Software programmable output range +5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 V INL error: 16 LSB maximum, DNL error: 1 LSB maximum Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 s typical Integrated reference buffers Output control during power-up/brownout Simultaneous updating via LDAC Asynchronous CLR to zero scale or midscale DSP-/microcontroller-compatible serial interface 24-lead TSSOP Operating temperature range: -40C to +85C iCMOS process technology1
GENERAL DESCRIPTION
The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial input, voltage output, digital-to-analog converters. They operate from single-supply voltages from +4.5 V up to +16.5 V or dualsupply voltages from 4.5 V up to 16.5 V. Nominal full-scale output range is software-selectable from +5 V, +10 V, +10.8 V, 5 V, 10 V, or 10.8 V. Integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry are also provided. The parts offer guaranteed monotonicity, integral nonlinearity (INL) of 16 LSB maximum, low noise, and 10 s typical settling time. The AD5722/AD5732/AD5752 use a serial interface that operates at clock rates up to 30 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of Pin BIN/2sComp), and straight binary for a unipolar output. The asynchronous clear function clears all DAC registers to a user-selectable zero-scale or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the -40C to +85C industrial temperature range. The AD5722/AD5732/AD5752 are pin compatible with the AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/ 16-bit, serial input, unipolar/bipolar voltage output DACs.
APPLICATIONS
Industrial automation Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers
FUNCTIONAL BLOCK DIAGRAM
AVSS AVDD REFIN DVCC CLR BIN/2sCOMP SDIN SCLK SYNC SDO INPUT SHIFT REGISTER AND CONTROL LOGIC 12/14/16 12/14/16 DAC A VOUTA
AD5722/AD5732/AD5752
REFERENCE BUFFERS
INPUT REGISTER A
DAC REGISTER A
INPUT REGISTER B
12/14/16 DAC REGISTER B
DAC B
VOUTB
GND
LDAC
DAC_GND (2)
SIG_GND (2)
Figure 1.
1
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS(R) is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
06467-001
AD5722/AD5732/AD5752 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Performance Characteristics ................................................ 5 Timing Characteristics ................................................................ 5 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings ............................................................ 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 18 Architecture ................................................................................. 18 Serial Interface ............................................................................ 18 Load DAC (LDAC)..................................................................... 20 Asynchronous Clear (CLR) ....................................................... 20 Configuring the AD5722/AD5732/AD5752 .......................... 20 Transfer Function ....................................................................... 20 Input Shift Register .................................................................... 24 DAC Register .............................................................................. 25 Output Range Select Register ................................................... 25 Control Register ......................................................................... 26 Power Control Register.............................................................. 26 Design Features ............................................................................... 27 Analog Output Control ............................................................. 27 Power-Down Mode .................................................................... 27 Overcurrent Protection ............................................................. 27 Thermal Shutdown .................................................................... 27 Applications Information .............................................................. 28 +5 V/5 V Operation ................................................................ 28 Layout Guidelines....................................................................... 28 Galvanically Isolated Interface ................................................. 28 Voltage Reference Selection ...................................................... 28 Microprocessor Interfacing ....................................................... 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5722/AD5732/AD5752 SPECIFICATIONS
AVDD = 4.5 V 1 to 16.5 V; AVSS = -4.5 V1 to -16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 k; CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter ACCURACY Resolution AD5752 AD5732 AD5722 Total Unadjusted Error (TUE) B Version A Version Integral Nonlinearity (INL)2 AD5752 A, B Versions AD5732 A Version AD5722 A Version Differential Nonlinearity (DNL) Bipolar Zero Error Bipolar Zero TC3 Zero-Scale Error Zero-Scale TC3 Offset Error Offset Error TC Gain Error Gain Error3 Gain Error3 Gain TC3 DC Crosstalk3 REFERENCE INPUT3 Reference Input Voltage DC Input Impedance Input Current Reference Range OUTPUT CHARACTERISTICS3 Output Voltage Range Headroom Required Output Voltage TC Output Voltage Drift vs. Time Short-Circuit Current Load Capacitive Load Stability DC Output Impedance Min Typ Max Unit Test Conditions/Comments Outputs unloaded
16 14 12 -0.1 -0.3 -16 -4 -1 -1 -6 4 -6 4 -6 4 -0.025 -0.065 0 4 120 2.5 5 0.5 +0.025 0 +0.08 +6 +6 +0.1 +0.3 +16 +4 +1 +1 +6
Bits Bits Bits % FSR % FSR LSB LSB LSB LSB mV ppm FSR/C mV ppm FSR/C mV ppm FSR/C % FSR
All models, all versions, guaranteed monotonic TA = 25C, error at other temperatures obtained using bipolar zero TC TA = 25C, error at other temperatures obtained using zero-scale TC TA = 25C, error at other temperatures obtained using zero-scale TC 10 V range, TA = 25C, error at other temperatures obtained using gain TC +10 V and +5 V ranges, TA = 25C, error at other temperatures obtained using gain TC 5 V range, TA = 25C, error at other temperatures obtained using gain TC
ppm FSR/C V V M A V V V V ppm FSR/C ppm FSR mA k pF 1% for specified performance
1 -2 2 -10.8 -12
+2 3 +10.8 +12 0.9
AVDD/AVSS = 11.7 V min, REFIN = +2.5 V AVDD/AVSS = 12.9 V min, REFIN = +3 V
0.5 4 50 20 2
Drift after 1000 hours of lifetest @ 125C For specified performance
4000 0.5
Rev. 0 | Page 3 of 32
AD5722/AD5732/AD5752
Parameter DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS (SDO)3 Output Low Voltage, VOL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS AVDD AVSS DVCC Power Supply Sensitivity3 VOUT/VDD AIDD AISS DICC Power Dissipation Power-Down Currents AIDD AISS DICC
1 2
Min 2
Typ
Max
Unit V V A pF V V V V A pF
Test Conditions/Comments DVCC = 2.7 V to 5.5 V, JEDEC compliant
0.8 1 5 0.4 DVCC - 1 0.4 DVCC - 0.5 -1 5 +1
Per pin Per pin DVCC = 5 V 10%, sinking 200 A DVCC = 5 V 10%, sourcing 200 A DVCC = 2.7 V to 3.6 V, sinking 200 A DVCC = 2.7 V to 3.6 V, sourcing 200 A
4.5 -4.5 2.7 -65
16.5 -16.5 5.5
V V V dB mA/channel mA/channel mA/channel A mW mW A A nA
0.5
3.25 2.4 2.5 3 190 79
Outputs unloaded AVSS = 0 V, outputs unloaded Outputs unloaded VIH = DVCC, VIL = GND 16.5 V operation, outputs unloaded 16.5 V operation, AVSS = 0 V, outputs unloaded
40 40 300
For specified performance, the maximum headroom requirement is 0.9 V. INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752, the AD5732, and the AD5722, respectively. 3 Guaranteed by characterization; not production tested.
Rev. 0 | Page 4 of 32
AD5722/AD5732/AD5752
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.5 V1 to 16.5 V; AVSS = -4.5 V to -16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 k; CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter2 DYNAMIC PERFORMANCE Output Voltage Settling Time Min Typ 10 7.5 3.5 13 35 10 10 0.6 15 80 320 Max 12 8.5 5 Unit s s s V/s nV-sec mV nV-sec nV-sec nV-sec V p-p V rms nV/Hz Test Conditions/Comments 20 V step to 0.03% FSR 10 V step to 0.03% FSR 512 LSB step settling (16-bit resolution)
Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Crosstalk DAC-to-DAC Crosstalk Digital Feedthrough Output Noise 0.1 Hz to 10 Hz Bandwidth 100 kHz Bandwidth Output Noise Spectral Density
1 2
0x8000 DAC code Measured at 10 kHz, 0x8000 DAC code
For specified performance, the maximum headroom requirement is 0.9 V. Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V; AVSS = -4.5 V to -16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 k; CLOAD = 200 pF; all specifications tMIN to tMAX, unless otherwise noted. Table 3.
Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t154 t164 t17
1 2 3
Limit at tMIN, tMAX 33 13 13 13 13 100 5 0 20 20 20 10 20 2.5 13 40 200
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min s max ns min s max ns min ns max ns min
Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Minimum SYNC high time (write mode) Data setup time Data hold time LDAC falling edge to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low DAC output settling time CLR pulse width low CLR pulse activation time SYNC rising edge to SCLK falling edge SCLK rising edge to SDO valid (CL SDO5 = 15 pF) Minimum SYNC high time (readback/daisy-chain mode)
Guaranteed by characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 CL SDO = capacitive load on SDO output.
Rev. 0 | Page 5 of 32
AD5722/AD5732/AD5752
TIMING DIAGRAMS
t1
SCLK 1 2 24
t6 t4
SYNC
t3
t2 t5
t7
SDIN DB23
t8
DB0
t9
LDAC
t10
t11
t12
VOUTx
t12
VOUTx
CLR
t13
t14
06467-002
VOUTx
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t17 t4
SYNC
t3
t2
t5 t15
t7
SDIN D32B
t8
D0B D32B D0B
INPUT WORD FOR DAC N
t16
DB23
INPUT WORD FOR DAC N - 1
DB0
SDO
UNDEFINED
INPUT WORD FOR DAC N
t10
t11
06467-003
LDAC
Figure 3. Daisy-Chain Timing Diagram
Rev. 0 | Page 6 of 32
AD5722/AD5732/AD5752
SCLK
1
24
1
24
t17
SYNC
SDIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ
NOP CONDITION
SDO
DB23
DB0
DB23
DB0
06467-004
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. 0 | Page 7 of 32
AD5722/AD5732/AD5752 ABSOLUTE MAXIMUM RATINGS
TA = 25C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
Parameter AVDD to GND AVSS to GND DVCC to GND Digital Inputs to GND Digital Outputs to GND REFIN to GND VOUTA or VOUTB to GND DAC_GND to GND SIG_GND to GND Operating Temperature Range, TA Industrial Storage Temperature Range Junction Temperature, TJ max 24-Lead TSSOP Package JA Thermal Impedance JC Thermal Impedance Power Dissipation Lead Temperature Soldering ESD (Human Body Model) Rating -0.3 V to +17 V +0.3 V to -17 V -0.3 V to +7 V -0.3 V to DVCC + 0.3 V or 7 V (whichever is less) -0.3 V to DVCC + 0.3 V or 7 V (whichever is less) -0.3 V to +5 V AVSS to AVDD -0.3 V to +0.3 V -0.3 V to +0.3 V -40C to +85C -65C to +150C 105C 42C/W 9C/W (TJ max - TA)/ JA JEDEC industry standard J-STD-020 3.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 8 of 32
AD5722/AD5732/AD5752 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVSS NC VOUTA NC BIN/2sCOMP NC SYNC SCLK SDIN
1 2 3 4 5 6 7 8 9 24 AVDD 23 VOUTB
AD5722/ AD5732/ AD5752
22 NC 21 SIG_GND
20 SIG_GND TOP VIEW (Not to Scale) 19 DAC_GND 18 DAC_GND 17 REFIN 16 SDO 15 GND 14 DVCC 13 NC
LDAC 10 CLR 11 NC 12
NOTES 1. NC = NO CONNECT 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2, 4, 6, 12, 13, 22 3 5 Mnemonic AVSS NC VOUTA BIN/2sCOMP Description Negative Analog Supply. Voltage ranges from -4.5 V to -16.5 V. This pin can be connected to 0 V if output ranges are unipolar. Do not connect to these pins. Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 k, 4000 pF load. Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND. When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos complement. (For unipolar output ranges, coding is always straight binary.) Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog outputs. When this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin should not be left unconnected. Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable). Digital Supply. Voltage ranges from 2.7 V to 5.5 V. Ground Reference. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. Ground Reference for the Two Digital-to-Analog Converters (DACs). Ground Reference for the Two Output Amplifiers. Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 k, 4000 pF load. Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V. Negative Analog Supply Connection. Voltage ranges from -4.5 V to -16.5 V. This paddle can be connected to 0 V if output ranges are unipolar. The paddle can be left electrically unconnected provided that a supply connection is made at the AVSS pin. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance.
7 8 9 10
SYNC SCLK SDIN LDAC
11 14 15 16 17 18, 19 20, 21 23 24 25 (EPAD)
CLR DVCC GND SDO REFIN DAC_GND SIG_GND VOUTB AVDD Exposed Paddle (EPAD)
Rev. 0 | Page 9 of 32
06467-005
AD5722/AD5732/AD5752 TYPICAL PERFORMANCE CHARACTERISTICS
6 4 2 0 -2 -4 -6 -8 0 10,000 20,000 30,000 CODE 40,000 50,000 60,000 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V 0.6 0.4 0.2
DNL ERROR (LSB)
INL ERROR (LSB)
0 -0.2 -0.4 -0.6 -0.8 0 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 10,000 = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V 20,000 30,000 CODE 40,000 50,000 60,000
06467-016
Figure 6. AD5752 Integral Nonlinearity Error vs. Code
1.5 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V
06467-013
Figure 9. AD5752 Differential Nonlinearity Error vs. Code
0.15 0.10
1.0
0.5
0.05
0
DNL ERROR (LSB)
INL ERROR (LSB)
0 -0.05 -0.10 -0.15 -0.20 0 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS 2000 = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V 6000 8000 CODE 10,000 12,000 14,000 16,000
06467-017
06467-018
-0.5
-1.0
-1.5
0
2000
4000
6000
8000 CODE
10,000 12,000 14,000 16,000
06467-014
-2.0
4000
Figure 7. AD5732 Integral Nonlinearity Error vs. Code
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V
Figure 10. AD5732 Differential Nonlinearity Error vs. Code
0.04 0.03 0.02 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V
DNL ERROR (LSB)
INL ERROR (LSB)
0.01 0 -0.01 -0.02 -0.03 -0.04
06467-015
-0.05 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
Figure 8. AD5722 Integral Nonlinearity Error vs. Code
Figure 11. AD5722 Differential Nonlinearity Error vs. Code
Rev. 0 | Page 10 of 32
AD5722/AD5732/AD5752
8 6 4
10 8 6
INL ERROR (LSB)
2 0 -2 -4
INL ERROR (LSB)
MAX INL 10V MAX INL 5V MIN INL 10V MIN INL 5V MAX INL +10V MIN INL +10V MAX INL +5V MIN INL +5V
4 2 0 -2 -4 -6 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX
-6 -8 -40
-8
06467-044
-20
0
20
40
60
80
6.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
Figure 12. AD5752 Integral Nonlinearity Error vs. Temperature
0.1 0 -0.1
Figure 15. AD5752 Integral Nonlinearity Error vs. Supply Voltage
1.0 0.8 0.6
BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX
DNL ERROR (LSB)
DNL ERROR (LSB)
-0.2
-0.3 -0.4 -0.5
MAX DNL 10V MAX DNL 5V MIN DNL 10V MIN DNL 5V MAX DNL +10V MIN DNL +10V MAX DNL +5V MIN DNL +5V
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
06467-045
-20
0
20
40
60
80
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
Figure 13. AD5752 Differential Nonlinearity Error vs. Temperature
10 8 6
Figure 16. AD5752 Differential Nonlinearity Error vs. Supply Voltage
1.0 0.8 0.6
BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX
DNL ERROR (LSB)
4
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
INL ERROR (LSB)
2 0 -2 -4 -6 -8
06467-034
BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
6.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 14. AD5752 Integral Nonlinearity Error vs. Supply Voltage
Figure 17. AD5752 Differential Nonlinearity Error vs. Supply Voltage
Rev. 0 | Page 11 of 32
06467-033
-10 11.5
-1.0 5.5
06467-032
-0.6 -40
-1.0 11.5
06467-035
-10 5.5
AD5722/AD5732/AD5752
0.02
6.0 5.5
0.01
5.0
0 BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX
4.5
AIDD (mA)
06467-036
TUE (%)
-0.01
4.0 3.5
-0.02
3.0
-0.03
2.5
-0.04 11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
6.5
8.5
10.5 AVDD (V)
12.5
14.5
16.5
SUPPLY VOLTAGE (V)
Figure 18. AD5752 Total Unadjusted Error vs. Supply Voltage
0.04 0.03
Figure 21. Supply Current vs. Supply Voltage (Single Supply)
4 +10V 3
ZERO-SCALE ERROR (mV)
0.02 0.01 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX
2 1
TUE (%)
0 -0.01 -0.02 -0.03 -0.04
10V
0 -1 -2 5V -3 -40
6.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
06467-037
-20
0
20
40
60
80
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
Figure 19. AD5752 Total Unadjusted Error vs. Supply Voltage
5 4 AIDD (mA)
0.8 0.6
Figure 22. Zero-Scale Error vs. Temperature
BIPOLAR ZERO ERROR (mV)
3 2 1 0 -1 -2 -3 -4 4.5 AIDD (mA)
0.4 5V RANGE 0.2 0 10V RANGE -0.2 -0.4 -0.6 -0.8
06467-047
AIDD/AISS (mA)
6.5
8.5
10.5 AVDD/AVSS (V)
12.5
14.5
16.5
06467-038
-1.0 -40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 20. Supply Current vs. Supply Voltage (Dual Supply)
Figure 23. Bipolar Zero Error vs. Temperature
Rev. 0 | Page 12 of 32
06467-046
-0.05 5.5
06467-042
2.0 4.5
AD5722/AD5732/AD5752
0.06 5V 0.04
15
10
0.02
OUTPUT VOLTAGE (V)
06467-048
GAIN ERROR (% FSR)
5
0
10V
0
-0.02 +10V -0.04
-5
-10
-20
0
20
40
60
80
-3
-1
1
3
5
7
9
11
TEMPERATURE (C)
TIME (s)
Figure 24. Gain Error vs. Temperature
1000 900 800
5 7
Figure 27. Full-Scale Settling Time, 10 V Range
600
OUTPUT VOLTAGE (V)
700
3
DICC (A)
500 400 300 200 100 DVCC = 3V 0 0 1 2 3 VLOGIC (V) 4 5 6
06467-043
1
DVCC = 5V
-1
-3
-5
-3
-1
1
3
5 TIME (s)
7
9
11
Figure 25. Digital Current vs. Logic Input Voltage
0.010
12
Figure 28. Full-Scale Settling Time, 5 V Range
0.005
OUTPUT VOLTAGE DELTA (V)
5V RANGE, CODE = 0xFFFF 10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF +5V RANGE, CODE = 0xFFFF 5V RANGE, CODE = 0x0000 10V RANGE, CODE = 0x0000
10
OUTPUT VOLTAGE (V)
0
8
-0.005
6
-0.010
4
-0.015
2
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-20
-15
-10
-5
0
5
10
15
20
25
-3
-1
1
3
5 TIME (s)
7
9
11
OUTPUT CURRENT (mA)
Figure 26. Output Source and Sink Capability
Figure 29. Full-Scale Settling Time, +10 V Range
Rev. 0 | Page 13 of 32
06467-024
-0.020 -25
0
06467-023
-100
-7
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-0.06 -40
-15
AD5722/AD5732/AD5752
6
5
OUTPUT VOLTAGE (V)
4
3
1
2
1
06467-025
-3
-1
1
3
5 TIME (s)
7
9
11
CH1 5V
M5s
LINE
73.8V
Figure 30. Full-Scale Settling Time, +5 V Range
Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth
0.020 0.015
0.10
10V RANGE, 0x7FFF TO 0x8000 10V RANGE, 0x8000 TO 0x7FFF 5V RANGE, 0x7FFF TO 0x8000 5V RANGE, 0x8000 TO 0x7FFF +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF +5V RANGE, 0x7FFF TO 0x8000 +5V RANGE, 0x8000 TO 0x7FFF
0.08 0.06
AVDD/AVSS = 16.5V AVDD = +16.5V, AVSS = 0V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.010 0.005
0.04 0.02 0 -0.02 -0.04 -0.06 -50
0 -0.005 -0.010 -0.015 -1
06467-027
0
RANGE = 5V RANGE = +5V
RANGE = +10V RANGE = 10V
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0
1
2 TIME (s)
3
4
5
-30
-10
10
30 TIME (s)
50
70
90
Figure 31. Digital-to-Analog Glitch Energy
15 10 5 0
Figure 34. Output Glitch on Power-Up
AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS
= +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V
TUE (LSB)
-5 -10 -15 -20 -25 -30
1
06467-026
0
1000
2000
3000 CODE
4000
5000
6000
CH1 5V
M 5s
LINE
73.8V
Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 35. AD5752 Total Unadjusted Error vs. Code
Rev. 0 | Page 14 of 32
06467-019
RANGE = 5V RANGE = +5V
RANGE = +10V RANGE = 10V
-35
06467-041
AD5722/AD5732/AD5752
4 2 AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V
1.0 0.5
AVDD/AVSS AVDD/AVSS AVDD/AVSS AVDD/AVSS = +12V/0V, RANGE = +10V = 12V, RANGE = 10V = 6.5V, RANGE = 5V = +6.5V/0V, RANGE = +5V
0
0
TUE (LSB)
-2
TUE (LSB)
06467-020
-0.5
-4
-1.0 -1.5
-6 -8
-2.0 -2.5 0 500 1000 1500 2000
CODE
0
2000
4000
6000
8000 CODE
10000 12000 14000 16000
2500
3000
3500
4000
Figure 36. AD5732 Total Unadjusted Error vs. Code
Figure 37. AD5722 Total Unadjusted Error vs. Code
Rev. 0 | Page 15 of 32
06467-021
-10
AD5722/AD5732/AD5752 TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 6. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5722/ AD5732/AD5752 are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 23. Bipolar Zero TC Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/C. Zero-Scale Error or Negative Full-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale - 1 LSB. A plot of zero-scale error vs. temperature can be seen in Figure 22. Zero-Scale TC Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale TC is expressed in ppm FSR/C. Output Voltage Settling Time Output voltage settling time is the amount of time required for the output to settle to a specified level for a full-scale input change. A plot for full-scale settling time can be seen in Figure 27. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/s. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal and is expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 24. Gain TC Gain TC is a measure of the change in gain error with changes in temperature. Gain TC is expressed in ppm FSR/C. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs.
Rev. 0 | Page 16 of 32
AD5722/AD5732/AD5752
DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in LSBs. Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec.
Rev. 0 | Page 17 of 32
AD5722/AD5732/AD5752 THEORY OF OPERATION
The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs. They operate from unipolar supply voltages of +4.5 V to +16.5 V or bipolar supply voltages of 4.5 V to 16.5 V. In addition, the parts have software-selectable output ranges of +5 V, +10 V, +10.8 V, 5 V, 10 V, and 10.8 V. Data is written to the AD5722/AD5732/ AD5752 in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy-chaining or readback. The AD5722/AD5732/AD5752 incorporate a power-on reset circuit to ensure that the DAC registers power up loaded with 0x0000. When powered on, the outputs are clamped to 0 V via a low impedance path.
REFIN R
R
R
TO OUTPUT AMPLIFIER
ARCHITECTURE
The DAC architecture consists of a string DAC followed by an output amplifier. Figure 38 shows a block diagram of the DAC architecture. The reference input is buffered before being applied to the DAC.
REFIN
R
R
06467-007
Figure 39. Resistor String Structure
Output Amplifiers
REF (+) DAC REGISTER RESISTOR STRING REF (-) VOUTX CONFIGURABLE OUTPUT AMPLIFIER
06467-006
The output amplifiers are capable of generating both unipolar and bipolar output voltages. They are capable of driving a load of 2 k in parallel with 4000 pF to GND. The source and sink capabilities of the output amplifiers can be seen in Figure 26. The slew rate is 3.5 V/s with a full-scale settling time of 10 s.
GND OUTPUT RANGE CONTROL
Reference Buffers
The AD5722/AD5732/AD5752 require an external reference source. The reference input has an input range of 2 V to 3 V, with 2.5 V for specified performance. This input voltage is then buffered before it is applied to the DAC cores.
Figure 38. DAC Architecture Block Diagram
The resistor string structure is shown in Figure 39. It is a string of resistors, each of value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
SERIAL INTERFACE
The AD5722/AD5732/AD5752 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI, QSPITM, MICROWIRETM, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2.
Rev. 0 | Page 18 of 32
AD5722/AD5732/AD5752
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. The input register addressed is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. When the data has been transferred into the chosen register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low while SYNC is high.
68HC11*
MOSI SCK PC7 PC6 MISO
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. Daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 x N, where N is the total number of AD5722/AD5732/AD5752 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data.
AD5722/ AD5732/ AD5752*
SDIN SCLK SYNC LDAC SDO
Readback Operation
Readback mode is invoked by setting the R/W bit = 1 in the write operation to the serial input shift register. (If the SDO output is disabled via the SDO disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again.) With R/W = 1, Bit A2 to Bit A0, in association with Bit REG2 to Bit REG0, select the register to be read. The remaining data bits in the write sequence are don't care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the DAC register of Channel A, the following sequence should be implemented: 1. Write 0x800000 to the AD5722/AD5732/AD5752 input register. This configures the part for read mode with the DAC register of Channel A selected. Note that all the data bits, DB15 to DB0, are don't care bits. Follow this with a second write, a NOP condition, 0x180000. During this write, the data from the register is clocked out on the SDO line.
SDIN
AD5722/ AD5732/ AD5752*
SCLK SYNC LDAC SDO
SDIN
AD5722/ AD5732/ AD5752*
SCLK SYNC LDAC SDO
06467-008
2.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy Chaining the AD5722/AD5732/AD5752
Rev. 0 | Page 19 of 32
AD5722/AD5732/AD5752
LOAD DAC (LDAC)
After data has been transferred into the input register of the DACs, there are two ways to update the DAC registers and DAC outputs. Depending on the status of both SYNC and LDAC, one of two update modes is selected: individual DAC updating or simultaneous updating of all DACs.
OUTPUT AMPLIFIER REFIN
CONFIGURING THE AD5722/AD5732/AD5752
When the power supplies are applied to the AD5722/AD5732/ AD5752, the power-on reset circuit ensures that all registers default to 0. This places all channels in power-down mode. The first communication to the AD5722/AD5732/AD5752 should be to set the required output range on all channels (the default range is the 5 V unipolar range) by writing to the output range select register. The user should then write to the power control register to power on the required channels. To program an output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are ignored. The AD5722/ AD5732/AD5752 operate with a wide power supply range. It is important that the power supply applied to the parts provide adequate headroom to support the chosen output ranges.
12-/14-/16-BIT DAC
VOUTX
LDAC
DAC REGISTER
INPUT REGISTER
TRANSFER FUNCTION
SDO
Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC
Individual DAC Updating
In this mode, LDAC is held low while data is clocked into the input shift register. The addressed DAC output is updated on the rising edge of SYNC.
06467-009
SCLK SYNC SDIN
INTERFACE LOGIC
Table 7 to Table 15 show the relationships of the ideal input code to output voltage for the AD5752, AD5732, and AD5722, respectively, for all output voltage ranges. For unipolar output ranges, the data coding is straight binary. For bipolar output ranges, the data coding is user selectable via the BIN/2sCOMP pin and can be either offset binary or twos complement. For a unipolar output range, the output voltage expression is given by
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is clocked into the input shift register. All DAC outputs are asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC.
D VOUT = VREFIN x Gain N 2
For a bipolar output range, the output voltage expression is given by
D VOUT = VREFIN x Gain N 2
- Gain x VREFIN 2
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low clear that allows the outputs to be cleared to either zero-scale code or midscale code. The clear code value is user-selectable via the CLR select bit of the control register (see the Control Register section). It is necessary to maintain CLR low for a minimum amount of time to complete the operation (see Figure 2). When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the CLR pin is low. A clear operation can also be performed via the clear command in the control register.
where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. VREFIN is the reference voltage applied at the REFIN pin. Gain is an internal gain whose value depends on the output range selected by the user, as shown in Table 6. Table 6. Internal Gain Values
Output Range (V) +5 +10 +10.8 5 10 10.8 Gain Value 2 4 4.32 4 8 8.64
Rev. 0 | Page 20 of 32
AD5722/AD5732/AD5752
Ideal Output Voltage to Input Code Relationship--AD5752
Table 7. Bipolar Output, Offset Binary Coding
Digital Input MSB 1111 1111 ... 1000 1000 0111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 5 V Output Range +2 x REFIN x (32,767/32,768) +2 x REFIN x (32,766/32,768) ... +2 x REFIN x (1/32,768) 0V -2 x REFIN x (1/32,768) ... -2 x REFIN x (32,766/32,768) -2 x REFIN x (32,767/32,768 Analog Output 10 V Output Range +4 x REFIN x (32,767/32,768) +4 x REFIN x (32,766/32,768) ... +4 x REFIN x (1/32,768) 0V -4 x REFIN x (1/32,768) ... -4 x REFIN x (32,766/32,768) -4 x REFIN x (32,767/32,768) 10.8 V Output Range +4.32 x REFIN x (32,767/32,768) +4.32 x REFIN x (32,766/32,768) ... +4.32 x REFIN x (1/32,768) 0V -4.32 x REFIN x (32,766/32,768) ... -4.32 x REFIN x (32,766/32,768) -4.32 x REFIN x (32,767/32,768)
Table 8. Bipolar Output, Twos Complement Coding
Digital Input MSB 0111 0111 ... 0000 0000 1111 ... 1000 1000 1111 1111 ... 0000 0000 1111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 5 V Output Range +2 x REFIN x (32,767/32,768) +2 x REFIN x (32,766/32,768) ... +2 x REFIN x (1/32,768) 0V -2 x REFIN x (1/32,768) ... -2 x REFIN x (32,766/32,768) -2 x REFIN x (32,767/32,768) Analog Output 10 V Output Range +4 x REFIN x (32,767/32,768) +4 x REFIN x (32,766/32,768) ... +4 x REFIN x (1/32,768) 0V -4 x REFIN x (1/32,768) ... -4 x REFIN x (32,766/32,768) -4 x REFIN x (32,767/32,768) 10.8 V Output Range +4.32 x REFIN x (32,767/32,768) +4.32 x REFIN x (32,766/32,768) ... +4.32 x REFIN x (1/32,768) 0V -4.32 x REFIN x (1/32,768) ... -4.32 x REFIN x (32,766/32,768) -4.32 x REFIN x (32,767/32,768)
Table 9. Unipolar Output, Straight Binary Coding
Digital Input MSB 1111 1111 ... 1000 1000 0111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 +5 V Output Range +2 x REFIN x (65,535/65,536) +2 x REFIN x (65,534/65,536) ... +2 x REFIN x (32,769/65,536) +2 x REFIN x (32,768/65,536) +2 x REFIN x (32,767/65,536) ... +2 x REFIN x (1/65,536) 0V Analog Output +10 V Output Range +4 x REFIN x (65,535/65,536) +4 x REFIN x (65,534/65,536) ... +4 x REFIN x (32,769/65,536) +4 x REFIN x (32,768/65,536) +4 x REFIN x (32,767/65,536) ... +4 x REFIN x (1/65,536) 0V +10.8 V Output Range +4.32 x REFIN x (65,535/65,536) +4.32 x REFIN x (65,534/65,536) ... +4.32 x REFIN x (32,769/65,536) +4.32 x REFIN x (32,768/65,536) +4.32 x REFIN x (32,767/65,536) ... +4.32 x REFIN x (1/65,536) 0V
Rev. 0 | Page 21 of 32
AD5722/AD5732/AD5752
Ideal Output Voltage to Input Code Relationship--AD5732
Table 10. Bipolar Output, Offset Binary Coding
Digital Input MSB 11 11 ... 10 10 01 ... 00 00 1111 1111 ... 0000 0000 1111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 5 V Output Range +2 x REFIN x (8191/8192) +2 x REFIN x (8190/8192) ... +2 x REFIN x (1/8192) 0V -2 x REFIN x (1/8192) ... -2 x REFIN x (8190/8192) -2 x REFIN x (8191/8191) Analog Output 10 V Output Range +4 x REFIN x (8191/8192) +4 x REFIN x (8190/8192) ... +4 x REFIN x (1/8192) 0V -4 x REFIN x (1/8192) ... -4 x REFIN x (8190/8192) -4 x REFIN x (8191/8192) 10.8 V Output Range +4.32 x REFIN x (8191/8192) +4.32 x REFIN x (8190/8192) ... +4.32 x REFIN x (1/8192) 0V -4.32 x REFIN x (1/8192) ... -4.32 x REFIN x (8190/8192) -4.32 x REFIN x (8191/8192)
Table 11. Bipolar Output, Twos Complement Coding
Digital Input MSB 01 01 ... 00 00 11 ... 10 10 1111 1111 ... 0000 0000 1111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 5 V Output Range +2 x REFIN x (8191/8192) +2 x REFIN x (8190/8192) ... +2 x REFIN x (1/8192) 0V -2 x REFIN x (1/8192) ... -2 x REFIN x (8190/8192) -2 x REFIN x (8191/8192) Analog Output 10 V Output Range +4 x REFIN x (8191/8192) +4 x REFIN x (8190/8192) ... +4 x REFIN x (1/8192) 0V -4 x REFIN x (1/8192) ... -4 x REFIN x (8190/8192) -4 x REFIN x (8191/8192) 10.8 V Output Range +4.32 x REFIN x (8191/8192) +4.32 x REFIN x (8190/8192) ... +4.32 x REFIN x (1/8192) 0V -4.32 x REFIN x (1/8192) ... -4.32 x REFIN x (8190/8192) -4.32 x REFIN x (8191/8192)
Table 12. Unipolar Output, Straight Binary Coding
Digital Input MSB 11 11 ... 10 10 01 ... 00 00 1111 1111 ... 0000 0000 1111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 +5 V Output Range +2 x REFIN x (16,383/16,384) +2 x REFIN x (16,382/16,384) ... +2 x REFIN x (8193/16,384) +2 x REFIN x (8192/16,384) +2 x REFIN x (8191/16,384) ... +2 x REFIN x (1/16,384) 0V Analog Output +10 V Output Range +4 x REFIN x (16,383/16,384) +4 x REFIN x (16,382/16,384) ... +4 x REFIN x (8193/16,384) +4 x REFIN x (8192/16,384) +4 x REFIN x (8191/16,384) ... +4 x REFIN x (1/16,384) 0V +10.8 V Output Range +4.32 x REFIN x (16,383/16,384) +4.32 x REFIN x (16,382/16,384) ... +4.32 x REFIN x (8193/16,384) +4.32 x REFIN x (8192/16,384) +4.32 x REFIN x (8191/16,384) ... +4.32 x REFIN x (1/16,384) 0V
Rev. 0 | Page 22 of 32
AD5722/AD5732/AD5752
Ideal Output Voltage to Input Code Relationship--AD5722
Table 13. Bipolar Output, Offset Binary Coding
Digital Input MSB 1111 1111 ... 1000 1000 0111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 5 V Output Range +2 x REFIN x (2047/2048) +2 x REFIN x (2046/2048) ... +2 x REFIN x (1/2048) 0V -2 x REFIN x (1/2048) ... -2 x REFIN x (2046/2048) -2 x REFIN x (2047/2047) Analog Output 10 V Output Range +4 x REFIN x (2047/2048) +4 x REFIN x (2046/2048) ... +4 x REFIN x (1/2048) 0V -4 x REFIN x (1/2048) ... -4 x REFIN x (2046/2048) -4 x REFIN x (2047/2048) 10.8 V Output Range +4.32 x REFIN x (2047/2048) +4.32 x REFIN x (2046/2048) ... +4.32 x REFIN x (1/2048) 0V -4.32 x REFIN x (1/2048) ... -4.32 x REFIN x (2046/2048) -4.32 x REFIN x (2047/2048)
Table 14. Bipolar Output, Twos Complement Coding
Digital Input MSB 0111 0111 ... 0000 0000 1111 ... 1000 1000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 5 V Output Range +2 x REFIN x (2047/2048) +2 x REFIN x (2046/2048) ... +2 x REFIN x (1/2048) 0V -2 x REFIN x (1/2048) ... -2 x REFIN x (2046/2048) -2 x REFIN x (2047/2048) Analog Output 10 V Output Range +4 x REFIN x (2047/2048) +4 x REFIN x (2046/2048) ... +4 x REFIN x (1/2048) 0V -4 x REFIN x (1/2048) ... -4 x REFIN x (2046/2048) -4 x REFIN x (2047/2048) 10.8 V Output Range +4.32 x REFIN x (2047/2048) +4.32 x REFIN x (2046/2048) ... +4.32 x REFIN x (1/2048) 0V -4.32 x REFIN x (1/2048) ... -4.32 x REFIN x (2046/2048) -4.32 x REFIN x (2047/2048)
Table 15. Unipolar Output, Straight Binary Coding
Digital Input MSB 1111 1111 ... 1000 1000 0111 ... 0000 0000 1111 1111 ... 0000 0000 1111 ... 0000 0000 LSB 1111 1110 ... 0001 0000 1111 ... 0001 0000 +5 V Output Range +2 x REFIN x (4095/4096) +2 x REFIN x (4094/4096) ... +2 x REFIN x (2049/4096) +2 x REFIN x (2048/4096) +2 x REFIN x (2047/4096) ... +2 x REFIN x (1/4096) 0V Analog Output +10 V Output Range +4 x REFIN x (4095/4096) +4 x REFIN x (4094/4096) ... +4 x REFIN x (2049/4096) +4 x REFIN x (2048/4096) +4 x REFIN x (2047/4096) ... +4 x REFIN x (1/4096) 0V +10.8 V Output Range +4.32 x REFIN x (4095/4096) +4.32 x REFIN x (4094/4096) ... +4.32 x REFIN x (2049/4096) +4.32 x REFIN x (2048/4096) +4.32 x REFIN x (2047/4096) ... +4.32 x REFIN x (1/4096) 0V
Rev. 0 | Page 23 of 32
AD5722/AD5732/AD5752
INPUT SHIFT REGISTER
The input shift register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) that must always be set to 0, three register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. Table 16 shows the register format, and Table 17 describes the function of each bit in the register. All registers are read/write registers. Table 16. Input Register Format
MSB DB23 R/W DB22 Zero DB21 REG2 DB20 REG1 DB19 REG0 DB18 A2 DB17 A1 DB16 A0 LSB DB15 to DB0 Data
Table 17. Input Register Bit Functions
Bit Mnemonic R/W REG2, REG1, REG0 Description Indicates a read from or a write to the addressed register. Used in association with the address bits to determine if a write operation is to the DAC register, the output range select register, the power control register, or the control register. REG2 REG1 REG0 Function 0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register These DAC address bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 1 0 DAC B 1 0 0 Both DACs Data bits.
A2, A1, A0
Data
Rev. 0 | Page 24 of 32
AD5722/AD5732/AD5752
DAC REGISTER
The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel in which the data transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5752 (see Table 18), DB15 to DB2 for the AD5732 (see Table 19), and DB15 to DB4 for the AD5722 (see Table 20). Table 18. Programming the AD5752 DAC Register
MSB R/W 0 Zero 0 REG2 0 REG1 0 REG0 0 A2 A1 DAC address A0 16-bit DAC data LSB DB15 to DB0
Table 19. Programming the AD5732 DAC Register
MSB R/W 0 LSB Zero 0 REG2 0 REG1 0 REG0 0 A2 A1 A0 DB15 to DB2 14-bit DAC data DB1 X DB0 X DAC address
Table 20. Programming the AD5722 DAC Register
MSB R/W 0 Zero 0 REG2 0 REG1 0 REG0 0 A2 A1 A0 DB15 to DB4 12-bit DAC data DB3 X DB2 X DB1 X LSB DB0 X
DAC address
OUTPUT RANGE SELECT REGISTER
The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, and the range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22). Table 21. Programming the Required Output Range
MSB R/W 0 Zero 0 REG2 0 REG1 0 REG0 1 A2 A1 A0 DB15 to DB3 Don't care DB2 R2 DB1 R1 LSB DB0 R0
DAC address
Table 22. Output Range Options
R2 0 0 0 0 1 1 R1 0 0 1 1 0 0 R0 0 1 0 1 0 1 Output Range (V) +5 +10 +10.8 5 10 10.8
Rev. 0 | Page 25 of 32
AD5722/AD5732/AD5752
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 23 and Table 24. Table 23. Programming the Control Register
MSB R/W 0 0 0 0 Zero 0 0 0 0 REG2 0 0 0 0 REG1 1 1 1 1 REG0 1 1 1 1 A2 0 0 1 1 A1 0 0 0 0 A0 0 1 0 1 DB15 to DB4 Don't care DB3 DB2 DB1 LSB DB0 SDO disable
NOP, data = don't care TSD enable Clamp enable CLR select Clear, data = don't care Load, data = don't care
Table 24. Explanation of Control Register Options
Option NOP Clear Load SDO Disable CLR Select Clamp Enable Description No operation instruction used in readback operations. Addressing this function sets the DAC registers to the clear code and updates the outputs. Addressing this function updates the DAC registers and, consequently, the DAC outputs. Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). See Table 25 for a description of the CLR select operation. Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an overcurrent; the current is clamped at 20 mA (default). Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent. Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Output CLR Value Bipolar Output Range 0V Negative full-scale
TSD Enable
Table 25. CLR Select Options
CLR Select Setting 0 1 Unipolar Output Range 0V Midscale
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5722/AD5732/AD5752. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register
MSB R/W 0 Zero 0 REG2 0 REG1 1 REG0 0 A2 0 A1 0 A0 0 DB15 to DB11 X DB10 0 DB9 OCB DB8 X DB7 OCA DB6 X DB5 TSD DB4 X DB3 X DB2 PUB DB1 X LSB DB0 PUA
Table 27. Power Control Register Functions
Option PUA PUB TSD OCA OCB Description DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an overcurrent and PUA is cleared to reflect this. DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an overcurrent and PUA is cleared to reflect this. Thermal shutdown alert (read-only bit). In the event of an overtemperature situation, both DACs are powered down and this bit is set. DAC A overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC A, this bit is set. DAC B overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC B, this bit is set.
Rev. 0 | Page 26 of 32
AD5722/AD5732/AD5752 DESIGN FEATURES
ANALOG OUTPUT CONTROL
In many industrial process control applications, it is vital that the output voltage be controlled during power-up. When the supply voltages change during power-up, the VOUTx pins are clamped to 0 V via a low impedance path (approximately 4 k). To prevent the output amplifiers from being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 42). These conditions are maintained until the power supplies have stabilized and a valid word is written to a DAC register. At this time, G2 opens and G1 closes.
VOLTAGE MONITOR AND CONTROL G1 VOUTA G2
06467-010
OVERCURRENT PROTECTION
Each DAC channel of the AD5722/AD5732/AD5752 incorporates individual overcurrent protection. The user has two options for the configuration of the overcurrent protection: constant current clamp or automatic channel power-down. The configuration of the overcurrent protection is selected via the clamp enable bit in the control register.
Constant Current Clamp (Clamp Enable = 1)
If a short circuit occurs in this configuration, the current is clamped at 20 mA. This event is signaled to the user by the setting of the appropriate overcurrent (OCX) bit in the power control register. Upon removal of the short-circuit fault, the OCX bit is cleared.
Automatic Channel Power-Down (Clamp Enable = 0)
If a short circuit occurs in this configuration, the shorted channel powers down and its output is clamped to ground via a resistance of approximately 4 k. At this time, the output of the amplifier is disconnected from the output pin. The short-circuit event is signaled to the user via the overcurrent (OCX) bits, and the power-up (PUX) bits indicate which DACs have powered down. After the fault is rectified, the channels can be powered up again by setting the PUX bits.
Figure 42. Analog Output Control Circuitry
POWER-DOWN MODE
Each DAC channel of the AD5722/AD5732/AD5752 can be individually powered down. By default, all channels are in power-down mode. The power status is controlled by the power control register (see Table 26 and Table 27 for details). When a channel is in power-down mode, its output pin is clamped to ground through a resistance of approximately 4 k, and the output of the amplifier is disconnected from the output pin.
THERMAL SHUTDOWN
The AD5722/AD5732/AD5752 incorporate a thermal shutdown feature that automatically shuts down the device if the core temperature exceeds approximately 150C. The thermal shutdown feature is disabled by default and can be enabled via the TSD enable bit of the control register. In the event of a thermal shutdown, the TSD bit of the power control register is set.
Rev. 0 | Page 27 of 32
AD5722/AD5732/AD5752 APPLICATIONS INFORMATION
+5 V/5 V OPERATION
When operating from a single +5 V supply or a dual 5 V supply, an output range of +5 V or 5 V is not achievable because sufficient headroom for the output amplifier is not available. In this situation, a reduced reference voltage can be used. For example, a 2 V reference voltage produces an output range of +4 V or 4 V, and the 1 V of headroom is more than enough for full operation. A standard value voltage reference of 2.048 V can be used to produce output ranges of +4.096 V and 4.096 V.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The iCoupler(R) family of products from Analog Devices, Inc., provides voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5722/AD5732/AD5752 makes them ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 43 shows a 4-channel isolated interface to the AD5722/AD5732/AD5752 using an ADuM1400. For further information, visit http://www.analog.com/icouplers.
MICROCONTROLLER SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT CONTROL OUT
V IA V IB V IC V ID
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5722/AD5732/AD5752 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5722/AD5732/AD5752 are in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5722/AD5732/AD5752 should have ample supply bypassing of a 10 F capacitor in parallel with a 0.1 F capacitor on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitor is the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5722/AD5732/AD5752 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as a data clock, should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (this is not required on a multilayer board that has a separate ground plane, but separating the lines does help). It is essential to minimize noise on the REFIN line because any unwanted signals can couple through to the DAC outputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to a ground plane, and signal traces are placed on the solder side.
ADuM1400*
ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE
V OA V OB V OC V OD
TO SCLK TO SDIN TO SYNC TO LDAC
06467-011
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. Isolated Interface
VOLTAGE REFERENCE SELECTION
To achieve optimum performance from the AD5722/AD5732/ AD5752 over their full operating temperature range, a precision voltage reference must be used. Thought should be given to the selection of a precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long-term drift, and output voltage noise. * Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. To minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR421, allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used to trim out temperatureinduced errors. The temperature coefficient of a reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient conditions. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight
*
*
Rev. 0 | Page 28 of 32
AD5722/AD5732/AD5752
* long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. Reference output voltage noise needs to be considered in high accuracy applications that have relatively low noise budgets. It is important to choose a reference with as low an output noise voltage as practical for the required system resolution. Precision voltage references such as the ADR431 (XFET(R) design) produce low output noise in the 0.1 Hz to 10 Hz range. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. For all interfaces, the DAC output update can be initiated automatically when all the data is clocked in, or it can be performed under the control of LDAC. The contents of the registers can be read using the readback function.
AD5722/AD5732/AD5752 to Blackfin(R) DSP Interface
Figure 44 shows how the AD5722/AD5732/AD5752 can be interfaced to the Analog Devices Blackfin DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5722/AD5732/AD5752 and the programmable I/O pins that can be used to set the state of a digital input such as the LDAC pin.
SPISELx SCK MOSI SYNC SCLK SDIN
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5722/AD5732/AD5752 is via a serial bus that uses a standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5722/ AD5732/AD5752 require a 24-bit data-word with data valid on the falling edge of SCLK.
ADSP-BF531
AD5722/ AD5732/ AD5752
LDAC
06467-012
PF10
Figure 44. AD5722/AD5732/AD5752 to Blackfin Interface
Table 28. Some Precision References Recommended for Use with the AD5722/AD5732/AD5752
Part No. ADR431 ADR421 ADR03 ADR291 AD780 Initial Accuracy (mV max) 1 1 2.5 2 1 Long-Term Drift (ppm typ) 40 50 50 50 20 Temp Drift (ppm/C max) 3 3 3 8 3 0.1 Hz to 10 Hz Noise (V p-p typ) 3.5 1.75 6 8 4
Rev. 0 | Page 29 of 32
AD5722/AD5732/AD5752 OUTLINE DIMENSIONS
7.90 7.80 7.70 5.02 5.00 4.95
24
13
4.50 4.40 4.30 6.40 BSC
1 12
EXPOSED PAD (Pins Up)
3.25 3.20 3.15
TOP VIEW 1.20 MAX 1.05 1.00 0.80 0.65 BSC 0.30 0.19
BOTTOM VIEW
8 0 0.20 0.09 0.75 0.60 0.45
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
Figure 45. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5722AREZ1 AD5722AREZ-REEL71 AD5732AREZ1 AD5732AREZ-REEL71 AD5752BREZ1 AD5752BREZ-REEL71 AD5752AREZ1 AD5752AREZ-REEL71
1
Resolution (Bits) 12 12 14 14 16 16 16 16
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to 85C -40C to 85C -40C to +85C -40C to +85C
INL 1 LSB 1 LSB 4 LSB 4 LSB 16 LSB 16 LSB 16 LSB 16 LSB
TUE (% FSR) 0.3 0.3 0.3 0.3 0.1 0.1 0.3 0.3
Package Description 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP 24-Lead TSSOP_EP
061708-A
SEATING PLANE 0.10 COPLANARITY
0.15 0.05
Package Option RE-24 RE-24 RE-24 RE-24 RE-24 RE-24 RE-24 RE-24
Z = RoHS Compliant Part.
Rev. 0 | Page 30 of 32
AD5722/AD5732/AD5752 NOTES
Rev. 0 | Page 31 of 32
AD5722/AD5732/AD5752 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06467-0-10/08(0)
Rev. 0 | Page 32 of 32

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